Simulation acceleration, also known as co-emulation, combines functional simulation with emulation hardware, or prototyping platforms to provide improved runtime performance over a pure simulation platform.
A test bench or testing workbench is an environment used to verify the correctness or soundness of a design or model. In the context of software or firmware or hardware engineering, a test bench is an environment in which the product under development is tested with the aid of software and hardware tools. The software may need to be modified slightly in some cases to work with the test bench but careful coding can ensure that the changes can be undone easily and without introducing bugs.
Behavioral code written in a hardware (HW) description language like Verilog/VHDL or a hardware verification language like System Verilog cannot be synthesized easily and thus cannot be used in emulation or hardware prototyping platforms. Hence, typically most test bench (or “testbench” herein) code which uses behavioral constructs executes on a simulator while the synthesizable code runs much faster in hardware. This is because execution is faster in the hardware and is also concurrent. As a result, the overall performance gains that can be expected through simulation acceleration are directly dependent on the time taken in simulation to execute the non-synthesizable code, as well as the overhead introduced as a result of the communication between the two partitions running on the simulator and in hardware.
Even for a transaction based acceleration where a part of a testbench runs on the hardware, the bottleneck is always on the simulator side. Besides the simulation platforms being evidently slower, the execution in a simulation platform is also single threaded. Whenever there are concurrent requests from the hardware platform (e.g., emulation hardware or FPGAs) to the simulation platform, the request events get pipelined in the simulator event queue and are processed sequentially (and slowly) by the simulation engine. This effectively brings down the potential gain that could have been obtained through simulation acceleration.